Sample and Hold Circuit

55-4920-430-13

(2) The resistance bridge consists of resistors R70, R71, and R74, with a variable resistance ele-

ment switch S14 connected between circuit card pins 29 and 21. An external resistance of 1.2 ohms

balances the bridge.

(3) The inputs of comparator U1 are connected across the bridge. With a resistance greater than

1.35 ohms between pins 21 and 29, the voltage on pin 3 of comparator U1, is greater than the voltage on

pin 2. Output voltage at pin 7 of U1 is negative. When the resistance between pins 21 and 29 is less than

1.2 ohms, the voltage on pin 2 of U1 is greater than the voltage on pin 3. In this case, output voltage

from pin 7 of U1 is positive. When U1 output is positive, the feedback thru resistor R73 maintains a

positive output voltage on pin 7 of U1 for resistances up to 1.35 ohms connected between pins 21 and

29.

(4) Transistor Q2 is a ground side switch which controls CONTINUITY TEST indicator DS15.

When the output at pin 7 of U1 is positive, NPN transistor Q2 conducts and CONTINUITY TEST in-

dicator DS15 comes on. For a negative comparator output, transistor Q2 does not conduct for a

resistance less than 1.2 ohms. An open circuit, more than 1.2 ohms, does not light DS15.

1-17. Sample and Hold Circuit. (See fig. 1-11.) Circuit card assembly A4 includes circuits for mak-

ing sample-and-hold time response measurements. The circuit consist of a time delay generator, sti-

mulus power switching relays, and the sample-and-hold amplifier. Two toggle switches and a five-

digit thumbwheel switch control the circuit. Hold status is displayed by HOLD indicator DS10.

a. Power Switching Relays Circuit. This circuit applies a step voltage, by mean of relays and a dc

stimulus signal, to the computer network to be tested.

(1) When mode switch S8 is at OFF, an open circuit exists at pin 20 of circuit card A5. This con-

nects pin 10 of or gate U11, to +5-volt dc through resistor R2. With +5-volt dc at pin 10, the output of

U11 at pin 8 is a logic 1. This signal is connected to the input of U16 at pins 1, 3, 5, and 13. With a

logic 1 at the input of buffer inverters U16, the logic 1 is invertered to give a logic 0 at the outputs. This

applies a ground to the windings of relays K1 through K5. The relays operate and apply power to the

stimulus circuit.

(2) When the MODE switch is set to ON ground is connected to pin 10 of or gate U11 through

connector pin 20. With a ground at pin 10 of U11, the logic 1 is changed to a logic 0. The output of

U16 is a logic 1, which removes the ground from the windings of relays K1 through K5. The relays are

released, removing the stimulus signals from the computer under test.

b. Time Delay Generator Circuit. The time delay generator consist of a 10-megahertz oscillator,

nine binary-coded-decimal (BCD) counters U3, U5, U8, U10, U13, U15, U17, U18, and U19, two pull-

up resistors U9 and U14, one gate of gate U2, and one half of flip flop U12 and U4.

(1) When STIM switch S7 is at APPLY and MODE switch S8 is at OFF. Power is applied to the

stimulus circuits. This loads the counter with the time delay setting and starts the count down. Latch

U2 is set, removing a clear, allowing U12 to change state and output a logic 1. The logic 1 from pin 5 is

applied to pin 2 of nand gate U2 when it is clocked by the l-kilohertz clock pulse from counter U3 pin

13.

(2) The 1-kilohertz clock pulses are routed to time delay counters U5, U10, U15, U18, and U19.

These count the 1-kilohertz pulses from U2 pin 3 down from the time delay setting until the counters

have all counted down to zero. At this point a logic 0 borrow pulse is produced at U5 pin 13. At the end

of the time delay interval, counter U5 outputs the logic borrow pulse from pin 13 to clock the input of

flip-flop U4 at pin 1, changing the state of U4.

(3) When flip-flop U4 changes state, the results area logic 0 at the Q output on pin 6. The logic 0

level signal is connected to sample-and-hold amplifier U7 pin 8, of the FET switch, opening the interval

switch to the sample-and-hold amplifier. The amplifier and hold capacitor C21 now hold the voltage

present at the input, just prior to the opening of the FET switch.

1-21