Figure 4-5. Tape Motion and Data Concept

TM 11-6625-3024-14/EE641-AC-MMA-010/E154 SYSEX/TO 33AA50-5-1-1

and a clock input to the Gap and CRC counters.

time. This is the time allotted for the transport to

The output of the Load Flip-Flop is at WP Clock

accelerate and de-accelerate between the writing

rate.

of data blocks. (See Figure 4-5, Tape Motion and

Data Concept.) The output of the counter is applied

Three timing functions are issued to the

to a star/stop latch. A DELAY ENABLED pulse

processor from the Clock and Format Generator

from the processor resets the latch, which enables

circuit card. They are used to sense data and gaps

the delay counter to start counting from the

in block mode.

selected time set into the start/stop delay switches.

When the counter reaches a full count, the output

1. DATA SENSE pulse informs the processor

from the counter sets the start/stop latch. This

that data is being received from the transport.

produces the TIME pulse to the processor. The

READ CLOCK is received from the transport only

TIME pulse informs the processor that data can

when data is received. The READ CLOCK pulses

now be written on tape.

are counted by the Data Sense Counter. When

eight READ CLOCK pulses have been counted

The 10 MHz clock provides an input to the Clock

before a SHORT GAP pulse is detected, a DATA

Rate Counter. The Clock Rate Switches provide a

SENSE pulse is issued to the processor.

preset input to the counter to determine a WP

CLOCK (Write Clock) time for the Exerciser. Each

2. SHORT GAP pulse informs the processor

time the counter reaches a full count, a 3 sec

that End-Of-Block has occurred in the data from

One-Shot is fired to produce the WP Clock pulse.

the transport. The Short Gap Counter is a 2-bit

The Load Flip-Flop is also enabled, which

counter. The WP CLOCK pulse steps the counter

produces a reset pulse to the Clock Rate Counter

Figure 4-5. Tape Motion and Data Concept

4-9