READ DATA (Circuit Card 1A2A6)

TM 11-6625-3024-14/EE641-AC-MMA-010/E154 SYSEX/TO 33AA50-5-1-1

Input Buffers. (Front panel test points are the input

on each clock pulse. When READ CLOCK is

signals from the transport.) The buffers convert the

received from transDort data, the counter is reset.

input data from negative to positive logic. The data

(WP CLOCK and READ CLOCK occur at the same

from the buffers is loaded into LRC Registers. The

rate, one clock period apart.) When READ CLOCK

READ CLOCK from the transport loads the data

is not received it is assumed that the Data Block

into the LRC Registers. The LRC error check is not

has ended. The Short Gap Counter will then count

made until the entire block of data has exercised

two WP CLOCK pulses and issue a SHORT GAP

the LRC Registers. During a block of data, an even

pulse to the processor.

number of ones will have appeared on each track.

Therefore, if no errors have occurred in the data

3. LONG GAP pulse informs the processor of

track, the LRC Registers will have toggled to a

LRC word time, When the processor receives a

reset state at the end of the data block. If an error

LONG GAP-pulse, it then issues the WRITE

did occur in a data track, the register for the error

RESET and DELAY ENABLED pulses. When a

track will toggle an odd number of times, leaving an

SHORT GAP is detected the Long Gap Counter is

error indication when LRC check is made at-the

enabled, counting WP CLOCK pulses. When the

end of block. LRC CHECK signal from the

counter has counted eight WP CLOCK pulses, a

processor enables the LRC Error-Gate and then

LONG GAP pulse is issued to the processor. A

resets all of the LRC Registers for the next block

READ CLOCK from the transport will inhibit the

of data.

Long Gap Counter from counting.

The eight bits of data are checked for parity error

END BLOCK signal from the Write Data Control

against the parity track from the transport.

circuit card starts the CRC Counter. When the

ENABLE ERROR signal is issued from the

counter has loaded three WP CLOCK pulses, a

processor enabling the error parity gate. An error

CRC WORD pulse is issued to the Write Data

output from the LRC or Parity Error gate will set the

circuit card. This enables the CRC WORD to be

respective error lamp, LRC ERROR or VRC

selected on the fourth data byte after END BLOCK

ERROR, indicating that an error has occurred.

has been issued. The CRC Counter continues to

Each time an error is detected on the output of

count to eight. At count eight a WRITE RESET

either error gate, an ERROR signal is issued to the

pulse is issued to the processor and the transport.

proessor. A CLEAR ERROR pulse is issued from

The eight count also resets the CRC Counter. The

the processor at the end of each data block, i.e.

data of the CRC word is selected (factory set) with

only one error sent to the processor will cause the

switches (U15) on the Read/Write circuit card.

processor to repeat a data block if REPEAT ON

ERROR is selected. All parity errors (VRC error)

4-7. READ DATA (Circuit Card 1A2A6) (See

are loaded into the SOFT ERROR counter and

Figure FO-5)

display. The display is enabled after each block of

The Read Data circuits receive the record data

data with an ENABLE pulse from the processor.

The HARD ERROR counter is loaded from the

from the transport. The data is checked for VRC

processor, The Repeat-On-Error mode will

(Vertical Redundancy Check) errors (parity error)

produce an error count when a block of data has

and LRC (Longitudinal Redundancy Check)

been repeated three times without recovery of the

errors. (See Figure 4-6, Read Data Block

Diagram.)

error. Therefore, the HARD ERROR counter and

display will count errors only in Block Mode and

Nine tracks of data are received from the

Repeat-On-Error mode.

transport (bits 0-7 and parity bit) and applied to

4-1o