SECTION IV. FUNCTIONAL DESCRIPTION

TM 11-6625-3024-14/EE641-AC-MMA-010/E154 SYSEX/TO 33AA50-5-1-1

SECTION IV

FUNCTIONAL DESCRIPTION

The Write Data Circuit Card receives the write

4-1. INTRODUCTION

data and adds the CRC WORD and shifted ones

when requested, and issues eight bits of parallel

This section provides an overall functional de-

data and parity bit to the transport.

scription of the Exerciser. The interrelationship of

the system's major components is discussed first,

The Data Control Select Circuit Card responds

followed by a more detailed functional description

to the data control switches on the front panel. The

of each major circuit.

selection of data is reported to the processor.

When the transport is in motion, the processor

4-2. SYSTEM DESCRIPTION

provides commands to the data control select

(See Figure FO-2)

circuits that prevent selection of new data until

transport motion has stopped.

The Exerciser provides write data and control

functions to the ECR-10 Transport for bench test

The Transport Status circuits receive status

operations. The Exerciser also receives the read

information from the transport to illuminate

data from the transport and checks the data for

indicators on the front panel. The Transport status

VRC (parity) and LRC errors. The Processor Cir-

information is also reported to the processor as

cuit Card controls the manipulation of data within

interrupt status.

the Exerciser, the generation of data, the record-

ing and testing of data from the transport and the

The Read Data circuits receive the reproduced

motion control of the transport.

data (READ DATA) from the transport. The data is

processed through an LRC check and a parity

The Processor Circuit Card circuits contain

check (VRC). The errors are accumulated and

programs in memory that respond to selected

displayed on two-digit LED displays. All errors are

switches on the front panel of the Exerciser. The

reported to the processor as an interrupt status.

processor also controls the timing for generation of

WRITE DATA. All commands from the motion

4-3. PROCESSOR (Circuit Card 1A2A3)

control switches on the front panel are issued to the

(See Figure FO-3)

processor. The processor performs timed routines

to check status of the transport before issuing the

The Processor Circuit Card contains the con-

motion control commands. The processor also

trolling circuits for the Exerciser. The processor

receives inputs from the data control switches and

uses a Signetics 2650 microprocessor as the cen-

then produces the appropriate control signals to

tral controller. (See Figure 4-1, Processor Block

generate the selected write data. All commands for

Diagram.) A basic understanding of microproces-

the writing and reading of data and motion

sors is required for a complete understanding of

selection for the transport communicate through

the Processor Circuit Card.

the processor.

The 2650 microprocessor is a general purpose,

The Clock and Format Generator Circuit Card

single chip, parallel 8-bit binary processor. The

generates the clock rate pulses for the system. It

processor performs data manipulations through

also establishes the timing for the generation of

execution of a stored sequence of machine

WRITE DATA and CRC WORD. The generator

instructions. The processor closely resembles

reports the timing sequence of the write data to the

conventional binary computers.

processor.

4-1