AC Stimulus and Self-Test Circuits

55-4920-430-13

(4) The counters continue counting and 2 seconds after the time delay interval, the QD output on

pin 7 of U10 goes to a logic 0 level as the digit transitions from eight to seven. Since the Q output of U4

pin 5, is already at logic 1, the logic 0 pulse from QD is applied to the clock input of U4. This changes

the state of the flip-flop, which changes the states of the outputs on connector pins 25 and 26. Q output

is now forward biased and will conduct the current of the hold light, which is connected externally to

+5-volt dc and the ground side is switched by turning on Q1. Output at pin 26 is a logic 0.

(5) The four bit BCD digit is loaded on the counter inputs, with D being the most significant bit

(MSD), and A the least significant bit (LSD). The counter inputs are connected to a +5-volt dc, through

pull-up-resistors U9 and U14, to form a logic 1 inputs. The BCD code is generated by grounding the

appropriate connector pins to the 5-volt dc return to form the logic 0 of the BCD code for each digit.

(6) Resistors R3, R4, R5 and capacitor 6 form an rc network with a time constant of 75 milli-

seconds. When relay K4 is energized this circuit is used for self-test to simulate a unit under test

response.

(7) The output at pin 9 of flip-flop U12 is set to logic 1 when the output from the buffer U16 pin 2

is at a logic 0, which occurs when the contacts of the relays K1 through K5 are closed. Whenever the Q

output pin 6 of flip-flop U4 is applied to the CLR input of flip-flop U12, the output at pin 9 of U12 is set

to 0. This condition will occur at the end of the time delay interval. The pulse produced at TP1 is a

pulse width equal to the time delay interval. When the MODE switch is set to OFF, the output of flip-

flop U12 pin 9 will be set to logic 0.

1. Therefore the first pulse at TP1 in the step response mode test mode (MODE switch to

ON) will not correspond to the time delay interval, the STIM switch must be first set to APPLY and

then to REMOVE. With the MODE switch remaining in the ON position, subsequent setting of the

STIM switch and TIME DELAY switches will produce a pulse on TP1 corresponding to the time delay

interval. Test point TP1 is from the Q output of flip-flop U12 at pin 9 and is used as a diagnostic aid to

check out and to debug the circuit card.

1-18. AC Stimulus and Self-Test Circuits. (See fig. 1-12. ) Circuit card assembly A5 includes cir-

cuits for generating 400 Hz ac stimulus signals and self-test signals. A5 includes the following circuits.

90 phase shift networks.

Voltage dividers.

DASH drive frequency dividers.

Continuity self-test circuits.

Logic stimulus circuits.

a. 90 Phase Shift Network.

(1) Connecting pin J1-18 to ground at P17-10 operates relay K1. The relay contacts connect the

13-volt ac signal from J1-2 and J1-32 to the 90 phase shift network and the voltage divider.

(2) The 90 lagging phase shift network includes resistors R1, R2, and R3 and capacitors C2 and

C3. With relay K1 operated, the 13-volt ac signal is applied to the input of the phase shift network. In

the network, the signal is shifted and lagged 90. The output of the network is about 4.36 volts. The

gain of amplifier U1 at pin 7 is 1.04. This is determined by voltage divider resistors R6 and R9. Am-

plifier U1 and resistors R7 and R8 form an inverter with unity gain. The output voltage at pin 8 is 4.5-

volt ac which leads the J1-2 input by 90.

(3) When relay K2 operates, the phase shifted signal is selected at connector pin 29. With a 13-

volt 400 Hz ac signal applied to pins J1-2 or J1-32 and connector pin J1-18 connected to ground at J1-

21, the voltage at J1-29 is 4.5-volt ac which is lagging the input by 90. When pin J1-24 is connected to

ground at J1-21, K2 is operated. With relay K2 operated, the 90 leading voltage is selected at pin J1-

29.