Microprocessing system description

TM 11-6625-2937-13

(2) Microprocessing system description. Under

location in that memory. This method of addressing

program control, the MPU (IA2A2) accesses memory by

uses the high order bits of the ADDRESS BUS to

outputting two, eight-bit bytes on the ADDRESS BUS.

generate CHIP SELECT, and the low order bits to

This 16-bit address, which permits access of 65,536

specify required memory location. When the appropriate

memory locations, is output via the three-state address

location has been selected, DO through D7 is output to

buffer (IA2A2). The address buffer outputs the address

the DATA BUS via data bus buffer (1A2A6). This DATA

information AO through Al5 on the ADDRESS BUS that

BUS output (through D7) can be input to the MPU under

connects the MPU (1A2A2) to the rest of the

test or to the STE MPU. Operation of the other memory

microprocessing system. That is, the ADDRESS BUS

devices is similar to the procedure just described in that

connects the MPU (IA2A2) to the STE RAM/ROM

they also are dependent on a two-level mode of

(IA2A3), the PIT and TEST ROM (IA2A6) and, via the

addressing and decoding for proper operation.

c. Phase-Locked Loop Functioning (fig. 4-4).

module bus switching circuit card (1A2A7), to the MPU

The phase-locked loop (PLL) consists of two channels,

under test. When not used to drive the ADDRESS BUS,

each of which provides a 4-MHz clock signal to

the address buffer (I A2A2) is switched into a high

MODULE TEST connector 12. This 4-MHz signal is

impedance state by control signal BA. TEST NUMBER

divided by four before feeding connectors J4 and J6.

(HCAO through HCA5) from the digital tester is decoded

UUT MICROPROCESSOR CLOCK and SYSTEM

by the NMI vector trap and is also output from the

CLOCK are applied to connector J2 from the PLL circuits

address bus. The MPU (I A2A2) also outputs control

simultaneously. The PLL circuit consists primarily of a

signals 02, R/W and VMA (VUA). These signals are

phase detector, a loop filter and a voltage-controlled

input to the three state control buffer (IA2A2) for output

oscillator

(VCO).

generate

the

UUT

to the CONTROL BUS. The control buffer (IA2A2)

MICROPROCESSOR CLOCK signal, the phase detector

operation is identical to the address buffer (IA2A2). The

requires a REFERENCE 250 KHZ signal from the digital

data buffer (1 A2A2) is a three-state bidirectional circuit

tester and a 250 KHZ CLOCK signal from the clock

that connects the data output from the MPU (DO through

feedback circuit (IA2A5). The phase detector output

D7) to the DATA BUS. The data buffer (IA2A2) acts as

voltage represents the difference in phase between the

an input buffer when data under READ control (R/W

input signals. After being coupled through the low pass

high) is input to the MPU. The buffer also acts as an

loop filter, this output voltage is input to the VCO as a dc

output device when the MPU (IA2A2) is driving the DATA

control voltage. The dc voltage applied to the VCO

BUS under WRITE control (R/W low). When other units

produces an output signal whose frequency is

are using the DATA BUS, the data buffer (IA2A2) is

determined by the voltage input from the loop filter. The

switched to the high impedance state. That is, data bus

SYSTEM CLOCK signal is also generated by a PLL that

buffer (IA2A7) is also a bidirectional device, but it is

receives a 250 KHZ input from a divide-by-16

either driven by the DO through 57 DATA BUS input from

divider/counter circuit. The divider/counter is reset by the

the control-interface unit or the MDO through MD7 DATA

RESET signal input from the digital tester. The SYSTEM

BUS input from the MPU under test. The control bus

CLOCK is divided down by 16 and outputs the 250 KHZ

buffer (IA2A7) and the address bus buffer (IA2A7) are

signal input to the PLL circuit. In the absence of the

both bidirectional devices. The operation of these

REFERENCE 250 KHZ signal, this PLL circuit will

devices is controlled by the STE MPU inputs to the bus

generate a simulated locked control voltage input to the

switching logic (1A2A7). The selection of a memory

VCO. This signal is generated via the loop lock

,device by the ADDRESS BUS (for reading or writing

simulator circuit when enabled by the 250 kHz dock

operations throughout the microprocessor system) is

detector. In normal operation, a portion of the phase

dependent on a decoder operation in conjunction with

detector outputs a digital 4W which is unaffected by the

the CONTROL BUS input. If, for example, the encoder

loop lock simulator circuit and is coupled to the phase

portion of the test ROM program is to be addressed, a

detector. In the absence of the IRERENCE 2SO KHZ

high ENC/DEC input is also necessary.. With the

signal, the loop lock simulator is enabled by the output

previous conditions satisfied, a two-level mode of

from the 250 KHZ dock detector circuit.

addressing occurs to select a particular memory device

and

the

appropriate

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