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TM 11-7010-201-40-1/ET821-AA-MMI-O1O/E154 MTS/T O 31S5-2TSQ73-2-1
a.
IIO Mast The I/O mask determines which probe signal lines are used for input and which are used for output.
The I/O mask also controls the probe control logic gates according to the CUT.
b.
Gross Card Type Decoder Logic The gross card type decoder logic accepts the card decode signal from the
memory address start location decoder logic. When enabled by the state 7 command, it generates a card group signal.
The timing and control function uses the card group signal to identify the CUT card group. The card groups are as
follows:
(1)
Card group a: cards with one circuit per card.
(2)
Card group b: card with six single-circuit ICs.
(3)
Card group c: cards with five single-circuit ICs.
(4)
Card group d: cards with six multiple-circuit ICs.
c.
Sliding Circuit Mask When enabled by an IC count pulse, the sliding circuit mask blocks off pins to all CUT
circuits except those pins connected to the circuit to be tested. This is accomplished through the probe function. Pin
masking is performed according to the CUT card group.
(1)
Card group a. When the CUT is in card group a, circuit masking is not required, since the CUT
contains only one circuit. The 1/0 mask identifies the required 1/0 pins of the CUT, and the sliding circuit mask is not
enabled during a cat d group a test.
(2)
Card group b. When the CUT is in card group b, circuit masking is required since the card contains
more than one IC. The IC count signal from the timing and control function allows the control logic to enable the probe
function. The probe function then enables the pins to the first IC of the CUT. When testing of the first IC is complete, the
IC count signal is advanced. This steps the control logic to enable the probe function, and the pins of the next IC of the
CUT. This process continues until all ICs on the CUT have been tested.
(3)
Card group c. The procedure for masking cards from card group c is identical to that described for card
group b.
(4)
Card group d. When the CUT is from card group d, more circuit masking is required since each IC on
the CUT contains more than one circuit. The IC count signal still allows the control logic to enable the probe function for
each IC on the CUT. This is the same action as that described for card group b. To provide a valid test, all circuits within
the IC (except the one being tested) must be masked by the memory. The address for the memory is derived from
application of the binary-coded card ID to the memory address start location decoder logic. The memory address start
location decoder logic generates a start location. This signal is loaded into the memory address generator logic, which
directly addresses the memory. The resulting memory mask, when applied to the control logic, enables testing of the first
circuit of each IC, and remains constant until each IC has been tested. At this time, the functional test timing signal
advances the memory address generator logic by one count. This changes the memory address applied to the memory.
The new memory mask corresponds to the next circuit in the ICs, and remains constant until that circuit in each IC is
tested. This process continues until all circuits of-all the ICs on the CUT have been tested.
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