CHAPTER 2. FUNCTIONING OF EQUIPMENT - TM-11-7010-201-40-10014

TM 11-7010-201-40-1/ET821-AA-MMI-010/E154 MTS/T O 31S5-2TSQ73-2-1

CHAPTER 2

FUNCTIONING OF EQUIPMENT

Section I. OVERALL FUNCTIONAL DESCRIPTION

2-1. Introduction.

This chapter provides a functional description of the Module Test Set (MTS).

The functional

description is presented in two levels: an overall functional description, and a detailed functional description. Section I

provides an overall description of how the MTS performs a card test, and covers the following topics: test sequence

initiation, continuity tests, functional tests, test sequence completion, and self-test operation. A block diagram of the

MTS is shown in figure 2-1.

2-2. Test Sequence Initiation. To perform circuit card identification, continuity tests, and functional tests, the MTS

compares data stored in its memory circuits with the outputs of the card under test (CUT). If the card data matches the

stored memory data, a passed card test (go condition) is indicated. If a mismatch in data occurs, a failed card test (no-go

condition) is indicated. During a card test, the MTS follows a set sequence of operations. This test sequence is started

by connecting the test set probe assembly to the card to be tested. A set of six card identification signals (card ID) is

applied by the probe function (see figure 2-1) to the timing and control function. There, the card ID is converted to a

seven-digit binary code. This binary code identifies the CUT to the MTS and starts the sequence timing. The test

sequence is a combination of manual and automatic operations.

These operations are explained in the following

paragraphs and flow charts. Table 2-1 illustrates flow chart symbology usage. Figure 2-2 is a flow chart showing how the

MTS advances step-by-step through a test sequence to accomplish card testing.

2-3. Continuity Test. Continuity testing of circuit cards checks for broken wires or pins in CUT signal paths. During

this test, the CUT is in the unit under test (UUT), and the UUT power is on. All signal lines on the CUT should be either a

logic ONE (high) or ZERO (low). Since all input pins on the CUT are connected to either a logic output or a pull-up

resistor, all logic outputs automatically assume a logic ONE or ZERO state. The MTS applies a 1.5 vdc basis to all

signal lines through the test set probe assembly. Each signal line should be greater than 2 vdc (for a logic one) or less

than 1 vdc (for a logic ZERO). Any line on the CUT showing less than 2 vdc and more than 1 vdc (i.e., approximately

1.5 vdc) is identified by the error detect logic as a continuity failure. Continuity test errors are displayed on the MTS front

panel according to which integrated circuit (IC) on the CUT has the continuity error. Each CONTINUITY ERROR indicator

identifies a group of lines in which the malfunction occurred. Each indicator represents 12 lines for cards having six ICs,

or 14 lines for cards having five ICs. The CONTINUITY ERROR indicators (left to right) correspond to the ICs (top to

bottom) on the CUT. Further isolation of the continuity error requires probing of connector J7 on the MTS front panel.

Some cards in the system have ICs with unused pins. Since these pins have no connection on the card or inside an IC,

the associated IC would normally fail any continuity test. However, the generated card ID is applied to a mask function

(see figure 2-1). The mask function generated an input/output (I/O) pin mask. The pin mask allows the unused pins to

pass the continuity test.

2-1