WRITE DATA CONTROL (Circuit Card 1A2A5)

TM 11-6625-3024-14/EE641-AC-MMA-010/E154 SYSEX/TO 33AA50-5-1-1

to zero. When the counter is started it will then

4-4. WRITE DATA CONTROL (Circuit Card

count a full block.

1A2A5) (See Figure FO-4)

When in block mode, the end of each block is

The generation of WRITE DATA starts with the

initiated when END BLOCK is set. An IRG (Inter

write data control circuits. (See Figure 4-2, Write

Record Gap) is then generated before the next

Data Control Block Diagram.)

block or the end of operation by a STOP command.

WRITE CLOCK pulses (CLOCK WP) from the

When BLOCK MODE is not selected, the mode is

clock generator circuit card are routed through a

continuous and the END BLOCK is not allowed

non-retriggerable delay circuit to the write data

until the STOP command has been set.

counter. The counter consists of a 28 counter (256

bits) and a divide-by-sixteen counter. The START

The WRITE DATA consists of 8 data bits and a

DATA issued from the processor resets the END

parity bit. The write data switches on the front panel

BLOCK latch, which enables the write card

can be individually enabled to select the logic level

counter. When the counter has reached a count of

for each bit. Switches are also provided on the front

256 (short block), a pulse is issued to the End Block

panel that will set the Write Data Latch to ALL 1,

Latch. The latch then produces the END BLOCK

ALL 0, or ALL PAT. When ALL PAT. switch is

signal to the format generator circuit card,

enabled, the data block pattern will be the pattern

indicating an end-of-block has occurred. When 4K

produced by the write data pattern counter. The

BLOCK has been selected on the front panel data

output of the Write Data Latches is applied to lamp

control switches, the 4K BLOCK IND signal from

drivers to illuminate the selected switch indicator.

the data control circuit card will inhibit the 256

Eight outputs from the write data pattern counter

pulse, allowing the divide-by-sixteen counter to

are combined with the appropriate bit from the

continue counting. After counting 4096, the

Write Data Latches into the Write Data Decoders.

counter will then issue a pulse to the End Block

The Write Data Decoders produce an 8-bit data

Latch. The END BLOCK signal will then be issued

block (WCO-WC7) and a parity bit (WPT). PARITY

to the format generator. The END BLOCK signal is

CHECK signal is produced from the write data

issued concurrently to the processor as an

circuit card.

indication of block mode status.

The first five bits of WRITE DATA (WCNTO-

The CLEAR DATA GEN signal is issued from the

WCNT4) are routed to the write data circuit card to

processor. This signal is issued before a START

be used in programming the SHIFTED ONES

DATA pulse to set the End Block Latch. The set

function.

condition of the End Block Latch provides a reset to

the write data pattern counter clearing the counter

4-4