Overall Block Diagram Analysis

TM 11-6625-2937-13

is applied to MODE SELECT switch S2, to power supply

OUTPUTS signal to the digital tester. This output signal

monitor (IA2AI) and connectors J1, 13 and JS.

is converted by the digital tester to a transition count for

Connectors J3, 13 and J5 are associated with encoder,

comparison with a transition count that has been stored

decoder and STE standard logic cards, respectively.

on the program card. This comparison results in the

Test data is obtained from the program card to set the

PASS/FAIL indication.

(6) Power distribution. Three-phase (115 V

TEST RATE PER SEC switch and the NUMBER OF

TESTS switch on the digital tester prior to inserting the

ac) power at 400 Hz is distributed via EMI filter FLI (IAI)

program card in the card reader slot. The digital tester

and circuit breaker CB1 (IA1) to front panel POWER

applies the proper stimulus for the STANDARD LOGIC

ON/OFF switch SI(1 A2). In the POWER ON position, 3

connectors with these switches set according to the

PHASE AC power is applied via the UNIT TEST ENC or

information printed on the program card, and with the

DEC position of MODE SELECT switch S2 (IA2) to UNIT

probe threshold switch set to 2 volts. After completing

TEST POWER connector JI 1. PHASE A power is

the digital tester setup, its input stimulus to the MODULE

applied, via front panel POWER ON/OFF switch SI, to

TEST connectors exercises a standard logic card. The

power supply PSI (1a1), power supply PS2 (1A1),

DIGITAL OUTPUTS signal from the standard logic card

POWER ON indicator DSI (1 A2), and ELAPSED TIME

are applied to the digital tester via the MODULE TEST

meter MI (IA2). PHASE A power is applied to power

connectors. This output signal is converted by the digital

supply PSI (1A1) and PS2 (1A1) to develop +5 V and i

tester to a transition count for comparison with a

15 V, respectively. Each dc output voltage is adjustable

transition count that has been input from the program

and protected by its own overvoltage protection circuit

card and stored in the digital tester. This comparison

(UI, U2 and U3, respectively), before application to circuit

results in the PASS/FAIL indication.

card connectors XA1 through XA12 (1A1) . Power

(4) Synchronization. The digital tester provides

supply PS3 (1A1) receives PHASE A input power from

a 250 KHz REFERENCE signal to the phase-locked loop

the UNIT TEST ENC or DEC position of MODE SELECT

(PLL) circuit (1A2A4) and the reset circuit (1A2AS). This

switch S2 (IA2) to provide +28V to UNIT TESTER

input signal synchronizes the PLL and is also applied via

POWER connector J11.

b. Microprocessor Functioning (FIG. 4-3). The

the reset circuit (IA2AS), which provides a RESET signal

to MODULE TEST connectors 12, J4 and J6

control interface unit and the digital tester provide

(MICROPROCESSOR). The RESET signal assures that

address information, data signals and control signals to

a test card inserted in the MICROPROCESSOR

the microprocessing system. These signals are used by

connector is reset, and therefore capable of being

the MPU, under program control, to generate the control

synchronized to the digital tester. The 4-MHz clock

signals that provide for movement of data throughout the

outputs from the PLL, depending on the mode of

control interface unit, and test information to the module

operation, provide both the SYSTEM CLOCK (for the

under test. To do this the MPU uses three memories

encoder only) and the UUT MICROPROCESSOR

and the programmable interval timer (P1). The read

CLOCK for input to J2 of the MICROPROCESSOR card

only memory (ROM) contains the program of instruction

connection. This 4-MHz signal is divided by four before

and look-up tables (data constants) used by the STE

feeding connectors J4 and J6. Either signal is applied via

MPU to check mode switch settings and verify test

the appropriate MODULE TEST connectors (32, J4 or

number information. The random access memory

16), and is counted down to provide the 250 KHZ

(RAM) acts as a scratch pad memory and is used by the

CLOCK outputs which are fed back for comparison to

STE MPU and the MPU under test to store variable data.

the PLL circuit. Connector 32, 34 and 36 are associated

Under program control, the STE MPU and MPU under

with the encoder, decoder and STE processor cards,

test can read or change the contents of RAM, but not the

respectively. The STE internal system clock circuit

contents of ROM. In a typical operation, the STE MPU

provides the signals (4 MHz CLOCK and 20 MHz

stops accessing the program of instructions in the ROM,

CLOCK) used to synchronize the operation of the

after the verification check sets the PIT, and turns the

control-interface unit.

microprocessing system control over to the MPU under

(5) Bus switching. After mode verification has

test. The test ROM contains the program of instructions

been completed (para 4-2a(2)), STE MPU 1A2A2

and look-up tables used to validate the operation of the

executes the bus switching portion of the STE program

MPU under test. When the test is finished, the MPU

ROM (1A2A3). The STE MPU then sets up bus

under test stores the variable test information in RAM,

switching circuit 1A2A7 via SYSTEM CONTROL so that

stops accessing the program of instruction in the test

the MPU card under test may access the test ROM

ROM, and returns microprocessing system control to the

circuit (1A2A6) via the ADDRESS BUS, CONTROL BUS

STE MPU. The STE MPU also access the program of

and DATA BUS. The STE MPU (1A2A2) now disables

instructions in the ROM to perform the BITE test. The

itself until the end of the test ROM operation. The MPU

variable test data stored in RAM is also accessed during

card under test executes the test program contained in

operation of

the test ROM circuit (1A2A6) and provides the DIGITAL

4-6