Control Memory Function

TM 11-7010-201-40-1/ET821-AA-MMI-010/E154 MTS/TO 31S5-2TSQ73-2-1

d. Unused Pin Mast On receipt of the binary-coded card ID, the unused pin mask determines which pins have no

connection on the CUT. These pins are masked from any testing functions.

2-1 0. Control Memory Function. The address logic test pattern of the test pattern memory (X-address, Y-address, Y-

address stop) accepts the binary coded card ID from the timing and control function (see figure 2-5). The address test

pattern is used as an address to select the correct stored information corresponding to the CUT. The Y-address start

signal from the Y-address start location decoder logic (binary 1 to 63) is applied to the Y-address generator logic. This

occurs when the Y-address start signal is enabled by the state 7 signal (perform functional test). The Y-address

corresponding to the start location number is then generated. This address, along with the Y-address stop signal from

the Y-address stop location decoder logic, is applied to the card test complete detect logic. The Y-address generator

logic will advance one bit each time a new test pattern bit is used. When its output reaches the same number as the stop

location, and after that bit has been error checked, the card test complete logic notifies the timing and control function

that the circuit test is complete. The next circuit on the CUT is then enabled (by the timing and control function) and the

same test pattern is repeated. The test pattern will continue to repeat until the IC counter logic in the timing and control

function generates a card and self-test complete signal. The quantity-of-circuits-per-IC decode logic stores the number

of ICs to be tested. This logic also contacts the timing and control function through the number of circuits signal. The

card type decode logic determines the card type being tested. It also notifies the test clock generator (with the card type

signal) in the timing and control function if clocks are required for that card. The same logic supplies the error detect

function with comparison data (compare data) for error checking. At the same time (state 7), the binary X and Y

addresses are applied to the test pattern memory logic and the control word memory logic. The test pattern memory

logic reads the selected test pattern data to the probe function for application to the CUT. The control word memory logic

contains the number of clock pulses required for that functional test pattern. That number is transferred to the test clock

counter logic. When the full count is reached, the error detect function makes a comparison of the stored CUT data.

The full count signal is then transferred to the test clock generator (timing and control function) to stop the count.

2-11. Error Detect Function. The error detect function (see figure 2-6) is performed by 12 data comparator cards.

Each card consists of six comparison channels, two latching lamp drivers, two nonlatching lamp drivers, and a 64-word

by eight-bit programmable read-only memory (PROM). The PROM receives a six- bit control address corresponding to

the card ID from the card type decode logic. An eight-bit memory word (test control) is generated and applied to the data

comparison channels. This enables or inhibits the comparators and assigns data lines to the appropriate front panel

indicator. The probe data (up to 72 lines) is compared to the compare data from the control memory function in the data

comparison channels. The results (channel output signals) are applied to the latching lamp driver logic. If the channel

output is low, the comparison is favorable. If the channel output is high, a potential error condition exists. During state 3,

the timing and control function applies a strobe pulse to the latching lamp driver logic. If an error is present, the latch

switches. It then enables the corresponding front panel indicator(s) (CONTINUITY ERROR) with the error latch signal.

During state 7, the functional test timing signal from the timing and control function is applied to the latching lamp driver

logic. If an error is present, the latch is switched. The applicable front panel indicator (FUNCTIONAL INPUT ERROR or

FUNCTIONAL OUTPUT ERROR) is lighted.

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