Timing and Control Function-continued

TM 11 -7010-201-40-1 /ET821 -AA-MMI-01 O/E1 54 MTS/T O 31 S5-2TSQ73-2-1

State 6. The state 6 command (turn on probe power) notifies the logic control to turn on power in the probe

function. The logic control senses this condition (greater than 4.2 vdc) and enables state 7 with the state advance signal.

State 7 During state 7, several operations occur to accomplish functional testing of the CUT.

(1)

The state 7 pulse is transferred to the functional test timing generator. The functional test timing

generator then generates the basic timing signals for the functional test operations.

(2)

The state 7 pulse is applied to the control memory function and the mask function. This enables the

binary-coded card ID signal (through the control memory and mask functions logic) to identify the card type and circuit to

be tested. The mask function then masks off all pins on the card except those applicable to the circuit to be tested.

(3)

If the card is an input/output controller (IOC) card, it cannot be checked in the normal manner. In this

case, a control memory function output causes the IOC card error detect logic to sense the card type. The IOC card error

detect logic checks the CUT output (probe data IOC) for errors.

(4)

The IC counter logic receives decoded binary ID information (number of circuits) from the control

memory function. The IC counter logic also receives the card type (card group) from the mask function. The IC counter

logic advances the mask and control memory functions each time an IC test is complete (IC count). When all ICs on the

CUT have been tested, the IC counter logic output enables the control memory function. This returns a card test

complete signal to the state generator.

If the CUT requires clock signals for testing, the control memory function enables the test clock

generator (card type). One test clock pulse (1-microsecond pulse width) is genemted each MTS cycle. The specific

number of total clocks is determined by the control memory function. When that number is reached, the control memory

function sends a full count signal to stop the test clock generator.

(6)

If an error is detected during the tests, the error lamp logic is enabled by the error latch or IOC error

signal. This lights the applicable error indicator.

(7)

When the functional tests are completed, the IC counter logic function enables state 8 (card test

complete).

State 8. The state 8 command (turn off probe power) causes the logic control to turn off probe power. When

the logic control senses power is off (less than 1.7 vdc) the logic control state advance signal enables state 9.

State 9. The state 9 command (connect CUT) causes the logic control to reconnect the card to the UUT with

the card reed switch control signal. The probe function commands the reed switch to close. The reed switch closed signal

triggers a 47-millisecond delay one-shot. The one-shot output advances the state generator to state 10 with the delayed

state advance signal.

State 10. In state 10, testing is either continued for another cycle (CONTINUOUS CYCLE switch on, or

REPEAT CYCLE switch activated) or terminated. On receipt of the cycle control signal input, the logic control advances

the state counter to the appropriate state.

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