MOTION CONTROL (Circuit Card 1A2A4)

TM 11-6625-3024-14/EE641-AC-MMA-010/E154 SYSEX/TO 33AA50-5-1-1

4-10. MOTION CONTROL (Circuit Card 1A2A4)

pulse at the SYNC connector at the start of each

(See Figure FO-8)

block of data (see Figure FO-5).

The Motion Control circuits select the required

4-13. POWER DISTRIBUTION (See Figure

motion for the transport. (See Figure 4-9, Motion

FO-9)

Control Block Diagram.)

The Exerciser power consists of +28 volts reg-

The Motion Control switches are push-ON

ulated, + 5 volts #1 regulated, and + 5 volts #2

push-OFF type switches. When any of the RUN,

regulated. (See Power Supply Schematic, Figure

FAST, or REWIND motions have been selected,

FO-10.)

the latches are locked out from accepting another

motion until the STOP switch is enabled. All the

Primary power (115 vat) is applied to the Power

motion select latches are set and reset by com-

Supply Assembly (1A1) through connector J1. A

mands from the processor.

5 amp SLO-BLO fuse provides main power short

circuit protection.

The Latched outputs from the Motion Select

Latches are applied to the processor to indicate

An RFI line filter is inserted in series with the

the required motion. The latch outputs are also

primary power to filter out RFI (Radio Frequency

applied through open collector gates to Lamp Driv-

Interference) noise.

ers. The Lamp Drivers provide return path for the

28 Vdc indicator lamps. SELECT 1 IND through

A solid state relay (K1) provides switching ON

SELECT 4 IND, lines are routed directly to the

and OFF of primary power to the power supply

transport to enable select interlocks.

regulators. The solid state relay is energized

through the SYSTEM-ON/OFF switch, located on

4-11. EXTERNAL START (Block Mode only)

the Power Switch Assembly (Figure 4-10). When

(See Figure FO-5)

the SYSTEM-ON/OFF switch is pressed, 115 vac

primary power is applied to the control input of the

The External Start connector (J4) provides an

solid state relay. The control input (115 vac)

input for an external signal to start each block of

causes the input relay contact to close. The closed

data when BLOCK MODE is selected. A dc signal

contact routes the primary power to the three

greater than 2.5 Vdc (or open input) will turn on

power supply regulators.

a dual operational amplifier, producing two low

level remote start signals (REMOTE START 1 and

REMOTE START 2). The remote start signals are

The +5 volt regulators (+5V #1 and +5V

applied to the Status Select latch on the processor

#2) each contain a 4 amp fuse (F1 and F2) for

circuit card. The microprocessor scans each of

overvoltage protection. If the voltage from the reg-

the status inputs at programmed intervals. When

ulator exceeds 5.6 Vdc, an SCR in the regulator

the microprocessor detects a REMOTE START

is fired, causing the output voltage to short out.

1 or REMOTE START 2 signal (SENSE LINE is

The shorted output voltage will cause the fuse to

high), the Write Data circuits are enabled to start

blow.

generating the next block of data. The External

Start signal should be a continuous level (2.5 Vdc

The output of the three voltage regulators is

to 5.0 Vdc) to generate a continuous string of data

applied to the Connector Panel Assembly through

blocks. When the External Start signal is pulsed,

connector P4. (See Figure FO-11.)

the data blocks will be generated at the External

signal pulse rate.

+5 Vdc #1 and +5 Vdc #2 are routed from

the Output Connector Assembly through connec-

4-12. SYNC

tors J9/P9 to the mother board circuit board as-

sembly. (See Figure FO-12.) The +5 Vdc #1 line

The microprocessor produces a SYNC pulse

provides power for circuit cards No. 1, No. 5, and

(U44-16) concurrent with the start of each block

No. 6 through the mother board. The +5 Vdc

of data when BLOCK MODE is selected (see Fig-

#2 line provides power for circuit cards No. 2, No.

ure FO-3). The SYNC pulse is applied to an open

3, and No. 4 through the mother board. (See

collector buffer, producing a negative-going TTL

mother board decoupling circuit, Figure 4-11.)

4-14