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TM 11-6625-3024-14/EE641-AC-MMA-010/E154 SYSEX/TO 33AA50-5-1-1
The SHIFTED ONES mode is normally used to
4-5. WRITE DATA (Circuit Card 1A2A6) (See
check the transport for measurement of combined
skew and jitter.
The Write Data circuits receive the data block
The WRITE DATA (WDO-WD7) from the data
from the write data control circuits, adds the CRC
word selector is routed through output buffers to
word, and generates parity before issuing the write
the transport. The output buffers invert the data for
data to the transport. (See Figure 4-3, Write Data
negative logic input to the transport.
Block Diagram.)
The DATA BLOCK (WCO-WC7) from write data
Each data track is applied to a parity decoder to
control circuit card is applied to the data word
check for even parity of each data byte. The output
selector. The CRC WORD pulse from the format
of the parity decoder is issued to the write data
generator circuit enables the data word selector to
control circuits.
select the input from the CRC word switches. The
switches are pre-set to the determined CRC word.
Errors are inserted by enabling the front panel
The CRC word is written during one clock period.
switch, INSERT ERRORS. This is a momentary
switch that sets an error latch, which changes the
The SHIFTED ONES IND input is issued from
parity decoder to read odd parity. Since parity
the data control circuits and selects an input to the
should always be even, odd parity from the parity
data word selector from the shifted ones selector.
decoder is detected as an error. The next clock
WCNT-1 through WCNT-4 is a binary input to the
pulse resets the error latch.
shifted ones selector. The binary input will select
one output from the selector. Each time the binary
input changes, the selected output changes. Each
selected output produces a logic one to the data
word selector. This results in a shifted ones pattern
in the WRITE DATA, as shown below.
000001000
111111111
000000100
111111111
000000010
111111111
000000001
4-6

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