PROCESSOR (Circuit Card 1A2A3)-continued

TM 11-6625-3024-14/EE641-AC-MMA-010/E154 SYSEX/TO 33AA50-5-1-1

The R/W (Read/Write) output from the

The DATA BUSS forms an 8-bit hi-directional

microprocessor is the operation control signal that

data path in and out of the microprocessor. The

defines external operations. R/W is an input to the

direction of the data flow on the DATA BUSS is

function decoder for selection of input or output

indicated by the state of the R/W line. For write

operations,

t h e output b u f f e r s i n t h e

ports.

microprocessor output the data to the DATA

The WRITE PULSE (WRP) output from the

BUSS. For read operations, the buffers are

microprocessor is a timing signal that provides a

disabled and the data condition of the DATA BUSS

is sensed by the microprocessor. The signals on

positive-going pulse in the middle of each

requested write operation, and a continuous high

the DATA BUSS are true signals, i.e., a one is a

level during read operations. WRP is used to

high level and a zero is a low level. See Figure

enable the Function Decoder for the selected

FO-3 for microprocessor signals.

operation.

The ADDRESS BUSS is a 12-bit path out of the

The SENSE line (Status Input) is an in-

microprocessor and is used primarily to supply

memory address during memory operation. The

dependent input from the DATA BUSS that

receives single bit data from the Status Input port.

addresses remain valid as long as OPREQ

(Operation Request) is true (high).

The FLAG line (Data Out) provides a single bit

The OPREQ output from the microprocessor is

output to the selected output port.

the coordinating signal for the Function Decoder

1K ROM memory contains all the required

operation.

routines for the microprocessor. The ROM is

The INTREQ (Interrupt Request) input to the

addressed by the microprocessor and outputs its

data on the DATA BUSS. The Function Decoder

microprocessor is a means to change the flow of

enables one of four Output Latches for receipt of

program execution. When an INTREQ is received,

DATA BUSS information. One of the Output

the current instruction is completed before the

Latches transfers the data to the l/O ADDRESS

interrupt is serviced. When the microprocessor is

BUSS. Data on the I/O ADDRESS BUSS is used to

ready to accept the interrupt, it sets the INTACK

address one of the I/O ports. The microprocessor

(Interrupt Acknowledge) output to high. The

then outputs a data bit on the FLAG line. The FLAG

INTACK output is used by the microprocessor to

line data bit is outputed on the addressed I/O port.

respond to the interrupt. The INTACK is used to

When input status is requested, the l/O ADDRESS

enable tri-state buffers on the DATA BUSS,

BUSS selects one of 16 status input lines to be

providing a b o o t strap address to the

inputed on the SENSE line.

microprocessor.

The MEMORY/IO output from the micro-

Memory Data on the DATA BUSS is also applied

processor is one of the operation control signals

to output latches that provide control data directly

that defines external operations. M/IO which indi-

to the Exerciser circuits or the transport.

cates whether an operation is memory or I/O is

used to gate the Function Decoder.

4-2