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CHAPTER 4
PRINCIPLES OF OPERATION
signal is converted and compared to the transition count
4-1.
Overall System Operation
which is input to the digital tester from the program card.
a.  General. The control-interface unit of the
The transition count provides an accurate means of
test set group extends the capability of the digital tester
testing and troubleshooting, since the count which is
to test standard logic cards and microprocessor (MPU)
registered on the digital tester transition counts display is
cards that cannot normally be tested by the digital tester
an accurate indication of module pass/fail operation.
alone. This extended capability permits fault isolation to
(2) Synchronization.
The MPU under test
the component level to be accomplished on the ground
receives the UUT MICROPROCESSOR CLOCK input
station decoder printed circuit cards, the airborne
from the phase-locked loop (PLL).  The MPU divides
encoder printed circuit cards and the special test
down this input and generates the 250 KHZ CLOCK
equipment (STE) printed circuit cards. Functions of the
feedback signal to the PLL. This 250 KHZ CLOCK input
test set group are described at the block diagram level in
is compared by the PLL with the 250 KHZ REFERENCE
this chapter.  Refer to TM 11-6625-2951-13 for the
signal from the digital tester. If these signals are not in
functional description of the digital tester.
phase, the PLL voltage-controlled oscillator (VCO) is
b.  System Block Diagram Analysis (fig. 4-1).
adjusted so that synchronization between the digital
The standard logic cards and microprocessor (MPU)
tester  and  the  MPU  under  test  is  established.
cards of a subsystem which have failed a BITE test are
Synchronization between the encoder SYSTEM CLOCK
individually connected via the front panel (I A2)
signal and the control-interface unit is maintained by a
connectors to the test set group. The control-interface
similar PLL circuit.
unit provides the means for interfacing the digital tester
(3) System control.  STE MPU IA2A2 resets
to the standard logic cards and microprocessor (MPU)
the MPU under test and then outputs SYSTEM
cards that are not readily tested by the digital tester.
CONTROL. This signal is used to turn control over to
(1) Program card. To test a printed circuit card,
the MPU under test.  It also sets up the module bus
the applicable program card is selected and inserted into
switching circuit (1A2A7) by using the ROM portion of
the digital tester's card reader slot. Each program card
STE RAM/ROM I A2A3 to generate the appropriate
is a plastic card with a magnetic stripe containing the test
ADDRESS and CONTROL BUS signals. The STE ROM
program for a particular printed circuit card. With the
portion of STE RAM/ROM IA2A3 normally holds the
program card inserted in the card reader slot and the
instructions for all of the STE MPU I A2A2 operations.
module under test inserted in the STANDARD LOGIC
The MPU under test assumes control after all of the
connector (al, J3 or J5) or the MICROPROCESSOR
previous conditions have been satisfied. It accesses the
connector (J2, J4 or J6), a verification check is made to
test ROM portion of the PIT (programmable interval
ensure that the MODE input signal to the STE MPU
timer) and test ROM portion of the memory (I A2A6).
(1A2A2) agrees with the TEST NUMBER display on front
Test ROM I A2A6 provides the test stimulus from the
panel 1 A2. The read only memory (ROM) portion of
test program stored in this portion of the memory. The
STE RAM/ROM circuit card 1 A2A3 provides the
PIT in the control-interface unit is set to limit the amount
program that is accessed from memory by STE MPU I
of time that the test can run. The MPU under test then
A2A2 for the verification check.  After the verification
runs the actual test, checking the various memories and
check is completed, the digital tester outputs the
peripheral interfaces. Test results are then displayed on
STIMULUS signal to test the module inserted in the
the digital tester's front panel. A failure of any part of the
STANDARD LOGIC connector.  The logic inputs from
test produces a failure indication on the digital tester, and
the digital tester result in an exact and repeatable
displays a TEST NUMBER readout for the failed test on
number of logic transitions (changes in logic state) at
the control-interface unit. Even if the MPU being tested
each output of the module under test.  The module
fails to run, a failure indication occurs only after the
inserted in the MICROPROCESSOR connector receives
prescribed time set by the PIT has elapsed. The test set
its stimulus from the STE MPU IA2A2 via the ADDRESS
group takes control again to indicate the failure. Data
BUS, CONTROL BUS and DATA BUS. In either case,
pertaining to the failure is stored by the MPU under test
the module under test outputs the DIGITAL COUNTS
in the RAM portion of STE RAM/ROM 1A2A3.
signal  for  input  to  the  digital  tester.
This
4-1

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